On-Device NPU Terminology Cheat Sheet

* Reverse-engineered Apple M1 findings. A dash means no validated mapping in the reviewed sources.

Columns follow an approximate editorial order by platform reach. Hardware examples are generation-specific. Sources & Scope

01Hardware

Compute, conversion, memory, data movement and interconnects

Concept & meaning	MediaTekGenio MT8370	QualcommHexagon	AppleM1 Neural Engine	IntelCore Ultra 200S/HX	AMDXDNA / XDNA 2
Accelerator The neural-network accelerator as a whole. Family names identify hardware, not a common microarchitecture.	APU / APUSYSAI Processor Unit	Hexagon NPU	Neural Engine	Intel NPUCore Ultra	XDNA NPURyzen AI
Compute grouping How computing resources are grouped. A core, tile or engine has a different scope on each platform.	MDLA + VP6Specialized engines	Scalar + vector + tensorFused accelerators	Neural Engine core	NCE tileNeural Compute Engine	AI Engine tileSpatial array
Matrix / tensor engine Hardware that performs many multiply-accumulate operations for matrix products and convolutions.	MDLA convolution engineWithin the MDLA accelerator	HMXMatrix eXtension	MAC array^*Multiply-accumulate datapath	DPUData Processing Unit	AI Engine vector unitMatrix MAC operations
Compute precision Numeric formats used for multiply operands. Documented examples, not full support lists; accumulation and stored weights may use other formats.	Fix8 / Fix16 / FP16 / BF16MDLA; Fix = fixed point	FP16 (HMX V81 example)37-bit float accumulation	FP16 operands^*Wider accumulation reported	INT8 / FP16NPU 3 MAC arrays	INT8 / BF16XDNA 2: also Block FP16
Vector processor A programmable processor that applies one instruction across multiple data elements (SIMD).	VP6Vision-P6 DSP	HVXVector eXtensions	-	ACT-SHAVEActivation SHAVE DSP	AI Engine vector processorSIMD
Activation / elementwise Resources for pointwise arithmetic and activation functions. Fixed-function stages and programmable vector processors differ.	Element-wise engineWithin MDLA	HMX convert stateActivation operations	Elementwise / planar^*Activation lookup table	Activation FunctionInference-pipeline stage	AI Engine vector processorElementwise kernels
Numeric conversion Changes numeric representation or range through format conversion, rounding or saturation. Available operations differ.	EDMA numeric conversionF16 / F32	HMX convert transferScale / round for FP16 output	FP16 output rounding^*After accumulation	Data ConversionInference-pipeline stage	SRS path / to_vectorShift-round-saturate
Control & scheduling Logic that decodes or schedules work. These examples range from command engines to scalar processors.	CMDEMDLA command engine	Hexagon scalar core	Firmware scheduler^*Task queues	LEON schedulerDPU / ACT-SHAVE dispatch	RISC scalar processorInside each AI Engine tile
Local data memory Storage near the compute units for operands or intermediate data. Caches and scratchpads have different management rules.	VP6 data RAMLocal to the vector DSP	VTCMVector tightly coupled memory	On-chip SRAM^*Compiler-managed scratchpad	CMX SRAMConnection MatriX	Local data memoryCompute / mem tiles
Instruction storage Stores or caches code for programmable compute processors. Program RAM and hardware-managed instruction caches differ.	IMEM + instruction cacheVP6	L1 instruction cacheHexagon core	-	Shared instruction L2 cacheACT-SHAVE	Program memoryInside each compute tile
Data movement Hardware paths that transfer data between memory and compute resources; transfers may overlap computation.	EDMAExternal DMA; format conversion	VMEM loads / storesExternal DMA via AXI	Tile DMA / kernel DMA^*Operands, results and weights	DMA enginesDRAM / CMX transfers	Tile DMA / shim DMAMemory transfers
Interconnect Connections carrying data between engines and memory. Memory-mapped interfaces and streaming fabrics use different protocols.	APU NoCOn-chip network	AXI slave portExternal DMA interface	-	-	AXI stream switch fabricTile-to-tile streams
Layout transformation Changes tensor or vector element order. Dedicated transpose units, shuffle instructions and DMA addressing have different scopes.	Transpose engineC-W / Depth2Space / Space2Depth	HVX shuffle / dealvshuff / vdeal	Transpose configuration^*Task-descriptor fields	-	Tile DMA address generationto_stream / from_stream
Weight compression Compact weight representations reduce storage or transfer volume. Compression formats do not determine compute precision.	Compressed weightsMDLA; codec unspecified	-	Palette / sparse weights^*M1 native streaming formats	In-line weight decompressionDMA engines	-
Address translation Maps virtual or device addresses to physical memory. Processor MMUs and host IOMMUs serve different address spaces.	IOMMUAPUSYS memory path	Hexagon MMUProcessor address space	DART^*ANE IOMMU	MMUNPU memory path	Host IOMMUPASID-based isolation

02Programming Model

Execution, transfer records, tensor blocks and synchronization

Concept & meaning	MediaTekGenio MT8370	QualcommHexagon	AppleM1 Neural Engine	IntelCore Ultra 200S/HX	AMDXDNA / XDNA 2
Execution model How instructions or tasks express parallel work at the hardware boundary. These are distinct programming models.	VP6: VLIW + SIMDMDLA: command-driven	Hexagon / HVX: VLIWHMX: matrix instructions	Hardware task descriptors^*Register configuration	DPU / ACT-SHAVE workScheduled hardware tasks	Tile kernels + dataflowVLIW / SIMD within tiles
Transfer descriptors Records configuring a transfer or a combined compute/DMA task. Scope and record layout depend on the engine.	-	External DMA descriptorPolled by the scalar core	Hardware task descriptor^*Includes DMA configuration	vpu_dma_descriptorNPU37XX firmware record	Buffer descriptor (BD)Tile DMA transfer record
Tensor blocking Partitions of tensor data processed or transferred together. The blocked axes, formats and sizes differ.	-	Activation croutonHMX operand block	Output-channel group^*OCG	-	Tile / micro-tileKernel data blocks
Vector element selection Per-element comparison results used to select vector values. Architectural registers and API types are distinct levels.	-	Vector predicateQ registers / vmux	-	-	aie::maskVector element mask type
Synchronization Mechanisms that order compute and data transfers so a consumer uses data after its producer completes.	-	External DMA syncStore-release / descriptor polling	Task event masks^*Wait / signal fields	Hardware barriersTask dependencies	Hardware locksCore / DMA coordination

Notes

Apple: Independent Research

Marked entries summarize Bryngelson’s M1 reverse engineering. Event masks describe on-die ordering; the vector-processor and vector-selection entries remain unmapped.

Keep Tile Meanings Separate

Compute tiles are hardware. Croutons, output-channel groups and matrix tiles partition tensor data along different axes. Their sizes and scopes differ.

Precision Has Several Meanings

INT8 is 8-bit integer. FP16 and BF16 (bfloat16) differ; Block FP16 uses shared exponents. Operand, accumulator and stored-weight precision are separate.

Sources & Scope 27 references

Select “Show citations” to see the sources for each vendor term. Definitions summarize the common concept.

Hardware examples: MediaTek MT8370 (Genio), Qualcomm Hexagon V73 HVX and V81 HMX, Apple M1, Intel Core Ultra 200S / 200HX, and AMD XDNA / XDNA 2. These are documented examples, not a claim about every current device.
MediaTek entries describe the MT8370 APUSYS: MDLA and the VP6 vector DSP. The matrix-engine entry names the convolution engine inside MDLA; MDLA also contains command and non-convolution engines. The local RAM entry belongs to VP6. CMDE decodes MDLA commands. The datasheet says hardware programming uses MediaTek's SDK.
Qualcomm HVX means Hexagon Vector eXtensions; HMX means Hexagon Matrix eXtension. HVX V73 and HMX V81 are separate documentation examples. VMEM names vector load/store instructions, not a DMA engine. The external-DMA entries concern access through the V73 AXI slave port and explicit synchronization by the scalar core.
Intel DPU means Data Processing Unit, and ACT-SHAVE is the activation vector DSP. NCE tile, CMX, DMA and barrier details here follow the cited 200S / 200HX design. The execution row describes hardware work types, not an assertion of a public custom-kernel API.
AMD examples use AI Engine compute tiles and the Ryzen AI low-level programming guide. Compute, mem and shim tiles have different functions. Hardware locks coordinate buffer use; the software ObjectFifo abstraction is not a separate hardware engine.
Apple naming follows its M1 announcement. Entries marked * summarize independent reverse engineering in arXiv:2606.22283v2. They describe recovered hardware interfaces, not a supported custom-kernel API. Synchronization uses the recovered M1 task-descriptor event masks (section 36.3, p. 234). No cross-die predictions, inferred array dimensions, core counts or memory capacities are included.
Column order approximates platform reach, not measured NPU use. Counterpoint's Q2 2026 smartphone SoC shipments place MediaTek (31%) ahead of Qualcomm (23%) and Apple (19%); these totals include chips without the NPUs discussed here. TechInsights' 2025 AI-PC data places Intel ahead of AMD. Combining those markets is an editorial choice, not a measured five-way ranking.
Activation / elementwise compares functional roles: the MT8370 element-wise engine, HMX convert-state operations, recovered Apple elementwise/planar and activation-lookup configuration, Intel’s NPU 3 Activation Function stage, and AMD vector kernels. It does not imply identical supported operations or separate dedicated engines on every platform.
Tensor blocking names data partitions: the HMX activation crouton, Apple M1 output-channel group (Ch. 20, section 20.4, p. 120), and AMD logical tiles / kernel micro-tiles. An output-channel group is not an activation crouton, and none is a physical compute tile. No matching MediaTek or Intel term is asserted from the reviewed sources.
Vector element selection maps the V73 HVX Q-register / vmux mechanism to AMD’s aie::mask API type at the level of per-element comparison and selection. It does not assert a dedicated AMD predicate register file. MediaTek, Apple and Intel mappings remain unvalidated in these sources.
Address translation has distinct scopes: the APUSYS IOMMU, Hexagon processor MMU, recovered Apple ANE DART (Ch. 28, p. 179), Intel NPU 3 MMU, and AMD host-IOMMU / PASID isolation. PASID identifies an address-space context; it is not itself an address-translation engine. AMD’s firmware microcontroller MMU is a separate unit.
Instruction storage follows the programmable compute units: VP6 IMEM/instruction cache, Hexagon L1 instruction cache, ACT-SHAVE shared data/instruction L2 cache, and AMD tile program memory. Apple M1 task descriptors are configuration records; no equivalent compute-instruction store is mapped in this row. Firmware instruction storage is outside this comparison.
Layout transformation compares element reordering at different granularities: the MT8370 MDLA transpose engine, HVX register shuffle/deal instructions, recovered M1 transpose fields in the hardware task descriptor, and AMD DMA address generation. It does not imply identical transforms, arbitrary tensor-transpose support, or a separate transpose engine on every device. Intel’s Data Conversion diagram label alone does not establish a layout-transform mechanism.
Weight compression: MT8370 documents compressed-weight support without naming the codec; Intel documents in-line DMA weight decompression. The Apple research reports native M1 palette and sparse weight streaming (section 3.3, p. 15), with reconstruction before the multiply array. Other compressed formats may expand in memory first. No corresponding Qualcomm or AMD mechanism is inferred from their arithmetic data types.
Numeric conversion compares functional roles: EDMA F16/F32 conversion, the HMX convert-transfer output path, recovered M1 FP16 output rounding, Intel’s labeled Data Conversion pipeline stage, and AMD SRS / accum::to_vector. Integer shift-round-saturate and floating-point conversion have different rules; no common precision, rounding mode or saturation behavior is implied. Bit reinterpretation is a separate operation.
Interconnect examples have different scopes: the MediaTek APU NoC, the Hexagon AXI slave interface for external DMA, and AMD’s AXI stream switch fabric. A memory-mapped AXI port is distinct from an AXI stream network. No equivalent Apple or Intel fabric name is asserted from the reviewed sources; CMX is identified as SRAM in this sheet.
Transfer descriptors name low-level records. The V73 HVX manual mentions external DMA descriptor polling without specifying its record layout. The Apple M1 hardware task descriptor also configures compute. Intel’s vpu_dma_descriptor is the pinned NPU37XX firmware record; AMD BDs describe tile-DMA transfers and synchronization. These records have different formats and are separate from graph nodes and runtime launches.
Compute precision lists selected multiply-operand formats for the cited engines, not every supported type or a throughput comparison. MediaTek uses Fix8/Fix16 for fixed-point MDLA modes; VP6 FP32 is separate. The V81 HMX manual covers FP16 operands with a 37-bit floating-point accumulator and does not enumerate all HMX types. The M1 research reports FP16 operands and wider accumulation (sections 3.1-3.2, pp. 13-14); it does not establish an exact IEEE FP32 accumulator specification. Intel NPU 3 labels its MAC arrays INT8/FP16. AMD documents INT8 and bfloat16 modes for XDNA1/XDNA2, plus Block FP16 on XDNA2. BF16 means bfloat16, not Block FP16 or IEEE FP16. Block FP16 shares exponents across groups of values; some API shapes use multiple instructions. An API float type or a compressed INT4 weight stream alone does not prove native FP32 or INT4 multiply arithmetic.
Reviewed on October 20, 2026 against vendor documentation and the cited independent Apple research. The new Apple entries were checked against the paper; they were not independently reproduced on hardware.

01
MediaTek: MT8370 datasheet v1.2, pp. 46-52
MT8370-specific APUSYS, MDLA convolution/element-wise engines and CMDE, VP6 SIMD/VLIW and local RAM, EDMA, and the APUSYS IOMMU (Fig. 3-4, p. 48). VP6 IMEM/instruction cache (p. 49), MDLA transpose engine (pp. 50-51), and compressed-weight support (p. 47); the datasheet does not name its compression codec. Figure 3-4 labels the APU NoC; p. 51 lists EDMA F16-to-F32 and F32-to-F16 numeric conversion. MDLA arithmetic modes include Fix8, Fix16, FP16 and BF16 (p. 47); VP6 also has FP32, which is a separate engine (p. 49).
02
Qualcomm: Hexagon NPU architecture
Fused scalar, vector and tensor accelerators; scalar control and VLIW execution. Counts and capabilities vary by generation.
03
Qualcomm: Hexagon V73 HVX manual, pp. 8-19
HVX SIMD instructions, VLIW packets, vector contexts, VTCM, VMEM access and explicit synchronization of external AXI DMA; vector predicate Q registers and vmux selection (p. 15). The AXI slave port and scalar-core polling of external DMA descriptors are described on p. 18.
04
Qualcomm: Hexagon V81 HMX manual, pp. 3-16
HMX matrix-multiply/convolution coprocessor, operands in VTCM, internal accumulator registers, convert state and activation operations, and the activation crouton. V81 is separate from the V73 HVX example. Convert transfer reduces accumulator values for the FP16 output path and applies configured bias, scale, shaping and rounding (pp. 12-16). Internal feedback precision and the stored output format differ. The manual covers FP16 activation/weight operands (p. 5) and a 37-bit floating-point accumulator (pp. 9-12); this is not an exhaustive HMX datatype list.
05
Apple: M1 Neural Engine
Official Neural Engine and core naming for M1. The table does not equate these cores with the compute groupings recovered in independent research.
06
Spencer H. Bryngelson: Apple Neural Engine: Architecture, Programming, and Performance (arXiv v2)
Independent reverse engineering, revised 15 Oct 2026. M1 examples: MAC datapath, output-channel groups and activation lookup (Ch. 20); compiler-managed SRAM (Ch. 21); task descriptors, elementwise/planar configuration and DMA (Ch. 23); DART address translation (Ch. 28); firmware scheduling (Ch. 29); on-die event masks (section 36.3, p. 234). Research findings, not an Apple specification. M1 native palette/sparse weight streaming (section 3.3, p. 15); transpose lowering and task-descriptor configuration (Chs. 22-23, pp. 134, 143). M1 output rounding to FP16 (section 3.1, p. 13); hardware task descriptors include DMA configuration (section 23.3, pp. 143-144). Sections 3.1-3.2 (pp. 13-14) report FP16 multiply operands and a wider accumulator, described as FP32-class rather than an exact IEEE FP32 specification.
07
Intel: NCE subsystem, Core Ultra 200S / 200HX
NCE tiles, ACT-SHAVE, CMX dedicated SRAM, DMA engines, task barriers and workload FIFOs. The DMA engines support in-line weight decompression; no specific encoding is asserted here.
08
Intel: NCE controller and ACT-SHAVE, Core Ultra 200S / 200HX
LEON scheduler, DPU / ACT-SHAVE job dispatch and activation vector processors. Scoped to this NPU generation.
09
AMD: XDNA architecture
Spatial dataflow array of AI Engine tiles; vector and RISC scalar processors, local data/program memories, VLIW/SIMD and scheduled DMA.
10
AMD: AI Engine matrix multiplication, 2025.2
Matrix multiply and accumulate operations for AI Engine, including XDNA targets. The API wraps processor operations; it is not a separate hardware core. XDNA1/XDNA2 tables list INT8 and bfloat16 operand modes and XDNA2 block-floating-point modes. Some API shapes are emulated; the float-input modes use native bfloat16 multiplication rather than native FP32 multiplication.
11
AMD/Xilinx: Ryzen AI programming guide, MLIR-AIE 1.4.4
Compute, mem and shim tiles, stream switches, per-tile kernels and spatial dataflow. Explicitly covers Ryzen AI XDNA and XDNA 2.
12
AMD/Xilinx: DMA and hardware locks, MLIR-AIE 1.4.4
Tile DMA channels, buffer descriptors, hardware locks, and synchronization between compute and data movement. Names the AXI stream switch fabric and buffer descriptor (BD) chains.
13
Counterpoint: Smartphone AP-SoC share, Q2 2026
Shipment proxy for mobile column order: MediaTek 31%, Qualcomm 23%, Apple 19%. Counts all smartphone SoCs, not NPU-equipped devices or active NPU use.
14
TechInsights: AI PC processor share, 2025
AI-PC segment ordering places Intel ahead of AMD. Does not supply a combined phone/PC installed-base ranking.
15
Intel: NCE tile and DPU, Core Ultra 200S / 200HX
DPU (Data Processing Unit), MAC processing engines, and ACT-SHAVE resources within an NCE tile. ACT-SHAVE DSPs share a data and instruction L2 cache.
16
Intel: Arrow Lake S & HX briefing, NPU 3 architecture (p. 40)
The NPU 3 hardware diagram explicitly labels the MMU and the Activation Function stage within each inference pipeline. Scoped to Arrow Lake S/HX. The same diagram labels the Data Conversion stage. It explicitly labels the NPU 3 MAC arrays INT8/FP16.
17
AMD: AI Engine API basic types, 2025.2
aie::mask is the API type for vector element masks returned by comparisons. It is a software representation, not a claim of a dedicated predicate register file. The guide includes XDNA1 and XDNA2. Distinguishes bfloat16 vector elements, wider accumulator types and XDNA2 bfp16ebs8/bfp16ebs16 block vectors, which group mantissas under a block exponent.
18
AMD/Xilinx: Kernel library, MLIR-AIE 1.4.4
Vectorized elementwise add/mul and ReLU kernel examples. TensorLayout distinguishes the logical data tile (shape) from the kernel micro-tile (block), including matrix multiply operands. These are data and kernel concepts, distinct from hardware tiles.
19
Qualcomm: Hexagon V73 manual, pp. 69 and 82
Virtual-to-physical address translation in the Hexagon address space (p. 69) and the OS-programmed Hexagon MMU (p. 82). This processor-side MMU is distinct from a system IOMMU. The cache-memory section names the L1 instruction cache (p. 82).
20
AMD: NPU driver architecture, Linux kernel documentation
PASID-protected host access for XDNA partitions, the global IOMMU domain for privileged host buffers, and a separate microcontroller MMU for firmware isolation. Host translation and firmware translation have different scopes. Each compute tile has dedicated program and data memory.
21
AMD: AI Engine API masked selection, 2025.2
aie::select combines input values or vectors using a per-element mask. This establishes the selection role of the mask API separately from the basic-type definition.
22
AMD/Xilinx: DMA data-layout transformations, MLIR-AIE 1.4.4
AIE-ML tile DMAs transform layouts through multidimensional address generation. The to_stream / from_stream inputs describe producer read order and consumer write layout. These are DMA configurations, not a separate transpose processor.
23
Qualcomm: V73 HVX shuffle/deal instructions, pp. 203 and 218
vshuff / vdeal reorder vector elements; the cross-lane forms perform multiple-level transposes between element groups in two vectors. These are register-level instructions, not a general tensor DMA engine.
24
AMD: AI Engine API numeric conversions, 2025.2
accum::to_vector converts accumulator values to vector elements; integer conversion can shift, round and saturate. Reinterpretation with cast_to is a separate operation, and integer shift behavior does not apply to floating-point accumulators.
25
AMD/Xilinx: SRS hardware path, MLIR-AIE 1.4.4
The AIE vector-unit SRS (shift-round-saturate) path converts accumulators to vectors before store; the UPS path performs the reverse direction. Scoped to the guide’s AIE2 / AIE2P Ryzen AI examples.
26
Intel: NPU37XX DMA firmware descriptor (pinned compiler source)
The Intel-authored NPU37XX header defines vpu_dma_descriptor, including source/destination addresses, length, strides, next-link and barrier fields. This is a firmware record example, not a stable public custom-kernel API or a format shared by all NPU generations.
27
AMD: XDNA 2 Block FP16 announcement (June 2024)
Names Block FP16 support in the XDNA 2 NPU of Ryzen AI 300 Series processors. Used only to establish that format and generation; no accuracy or performance equivalence is asserted.

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