On-Device NPU Terminology Cheat Sheet
Hardware components and low-level programming concepts across five NPU families, with shared definitions, sources, and a downloadable poster.
Read more
Yuduo Wu
AI/ML inference, compilers, kernels, and accelerators.
-
2025–Now
Qualcomm, AI Hub
Developing compiler infrastructure, graph optimizations, NPU kernels, and runtime for efficient AI execution on Snapdragon platforms.
-
2019–2025
Apple, Core ML
Heterogeneous inference for Apple Silicon. Neural Engine compilers. Compiler infrastructure and optimizations. Open-weight LLM optimizations.
-
2013–2015
UC Davis
Parallel Computing (GPGPU) with John Owens. Co-author of Gunrock, a CUDA GPU graph library, distinguished paper at PPoPP 2016.
Earlier, distributed training (e.g., “ImageNet in 1 hour”) at NovuMind and cloud services at IBM Silicon Valley Lab.
CUDA Graphs, Fusion, and Megakernels
If CUDA Graphs already reduce kernel launch overhead, why build a megakernel? One measured H100 workload connects graph replay, local fusion, and retained tiles.
Read moreAI Accelerator Terminology Cheat Sheet
Hardware and low-level programming terms across NVIDIA GPUs, AMD Instinct GPUs, Google TPU and AWS Trainium, with scoped comparisons, primary sources and a downloadable poster.
Read more